Memories such as n-write/1-read port type of memories are at the core of network switches/switching units in any communication network. An n-write/1-read port memory typically include a memory unit of a certain size comprising a plurality of memory banks/modules, multiple (n) write ports/interfaces through which a plurality of pipelines may write to the memory, and one read interface through which data may be read from the memory. Here, each memory bank can be of certain size/depth (e.g., 4 k) accessible by a memory address and of certain width, which is the number of (e.g., 40) data bits at each memory address. For a non-limiting example, the data at each memory address can be a counter associated with the specific memory address.
During operation, multiple pipelines may try to concurrently access the memory via the write interfaces, wherein each of the pipelines carries a data packet to update/increment the data (e.g., counter) at a specific memory address. Under such a scenario, there may be competition or conflict among the pipelines since they may all attempt to access the same memory bank/location at the same time. Although it is possible to replicate and include in the memory multiple (instead of only one) memory units so that each of the multiple write interfaces may have its own dedicated memory unit to avoid such conflict, such memory replication may result in an increase in size of the overall memory design. For example, N memory units would be needed to accommodate N write interfaces, which cause problem for the memory design when N becomes large.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent upon a reading of the specification and a study of the drawings.